1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to a method and apparatus for compensating external supply voltage in integrated circuits to ensure that output will compensate for any variation from external voltage supply.
2. Description of the Prior Art
Integrated circuits often suffer from PVT variations, which can affect the delicate workings of the internal circuits. Integrated circuits therefore require compensating circuits, which work to counteract the effect of these PVT variations.
A related art compensation method monitors a supply voltage, and utilizes variations in the supply voltage to activate a compensation circuit. When the supply voltage falls below a certain threshold, the compensation circuit is activated, and then deactivated once the supply voltage returns to above the threshold. The compensation circuit works to bring a falling delay in the circuit closer to a rising delay. This is because rising and falling delays are affected by PVT variations to different extents.
Another related art compensation method uses a compensation circuit that controls a bias voltage input to the circuit elements so that a constant threshold voltage is achieved. The bias of PMOS elements and NMOS elements are controlled separately.
If PVT variations in both the PMOS and NMOS elements could be controlled by a same circuit, supply voltage could be compensated for more accurately. Circuit complexity would also be reduced.